f0d81ffd1c
which included commits to RCS files with non-trunk default branches. git-svn-id: svn://10.65.10.50/trunk@5403 c028cbd2-c16b-5b4b-a496-9718f37d4682
156 lines
3.3 KiB
ArmAsm
Executable File
156 lines
3.3 KiB
ArmAsm
Executable File
;
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; Copyright (C) 1990-1996 Mark Adler, Richard B. Wales, Jean-loup Gailly,
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; Onno van der Linden, Kai Uwe Rommel, Igor Mandrichenko, Sergio Monesi and
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; Karl Davis.
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; Permission is granted to any individual or institution to use, copy, or
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; redistribute this software so long as all of the original files are included,
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; that it is not sold for profit, and that this copyright notice is retained.
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;
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; sendbits.s for ARM by Sergio Monesi.
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r0 RN 0
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r1 RN 1
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r2 RN 2
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r3 RN 3
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r4 RN 4
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r5 RN 5
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r6 RN 6
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r7 RN 7
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r8 RN 8
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r9 RN 9
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sl RN 10
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fp RN 11
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ip RN 12
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sp RN 13
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lr RN 14
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pc RN 15
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AREA |C$$code|, CODE, READONLY
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; r1 = ....
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|__bi_buf|
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IMPORT bi_buf
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DCD bi_buf
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|__bi_valid|
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IMPORT bi_valid
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DCD bi_valid
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|__out_buf|
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IMPORT out_buf
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DCD out_buf
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|__out_size|
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IMPORT out_size
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DCD out_size
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|__out_offset|
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IMPORT out_offset
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DCD out_offset
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IMPORT flush_outbuf
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IMPORT |x$stack_overflow|
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DCB "send_bits"
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DCB &00,&00,&00
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DCD &ff00000c
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EXPORT send_bits
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send_bits
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LDR r2, [pc, #|__bi_valid|-.-8]
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LDR r2, [r2]
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RSB r3, r1, #16
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CMP r2, r3
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BLE send_part2
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LDR r3, [pc, #|__bi_buf|-.-8]
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LDR ip, [r3]
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ORR ip, ip, r0, LSL r2
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STR ip, [r3]
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LDR r2, [pc, #|__out_offset|-.-8]
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LDR r2, [r2]
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LDR r3, [pc, #|__out_size|-.-8]
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LDR r3, [r3]
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SUB r3, r3, #1
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CMP r2, r3
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BCS send_flush
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STMFD sp!, {r4-r6,lr}
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MOV r6, #1
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LDR r4, [pc, #|__out_buf|-.-8]
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LDR r4, [r4]
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AND r5, ip, #&FF
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STRB r5, [r4, r2]
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ADD r2, r2, #1
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MOV r5, ip, LSR #8
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STRB r5, [r4, r2]
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ADD r2, r2, #1
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LDR r4, [pc, #|__out_offset|-.-8]
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STR r2, [r4]
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B send_cont
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send_flush
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MOV r3, ip
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MOV ip, sp
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STMFD sp!, {r4-r6,fp,ip,lr,pc}
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SUB fp, ip, #4
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CMPS sp, sl
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BLLT |x$stack_overflow|
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MOV r4, r0
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MOV r5, r1
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MOV r0, r3
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MOV r1, #2
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BL flush_outbuf
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MOV r0, r4
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MOV r1, r5
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MOV r6, #0
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send_cont
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LDR r2, [pc, #|__bi_valid|-.-8]
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LDR r3, [r2]
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RSB r3, r3, #16
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LDR r4, [pc, #|__bi_buf|-.-8]
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MOV r5, r0, LSR r3
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STR r5, [r4]
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LDR r3, [r2]
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ADD r3, r3, r1
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SUB r3, r3, #16
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STR r3, [r2]
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CMP r6, #0
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LDMEQEA fp, {r4-r6,fp,sp,pc}^
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LDMNEFD sp!, {r4-r6,pc}^
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send_part2
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LDR r3, [pc, #|__bi_buf|-.-8]
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LDR ip, [r3]
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ORR ip, ip, r0, LSL r2
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STR ip, [r3]
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LDR r3, [pc, #|__bi_valid|-.-8]
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ADD r2, r2, r1
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STR r2, [r3]
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MOVS pc, lr
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DCB "bi_reverse"
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DCB &00,&00
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DCD &ff00000c
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EXPORT bi_reverse
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bi_reverse
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MOV r2, #0
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rev_cycle
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MOVS r0, r0, LSR #1
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ADCS r2, r2, r2
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SUBS r1, r1, #1
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BNE rev_cycle
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MOV r0, r2
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MOVS pc, lr
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END
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